Design Engineer (Integrated Circuit Verification) / Up to $4500

Location Changi, Singapore
Job reference BBBH83530_1572430113
Salary Negotiable
Consultant name Selina Lim Siew Yen
Consultant email
Consultant contact no. 65515298
EA License No. 02C3423
Consultant Registration No. R1333126

Key Skills and Qualification:

  • Develop and Review Test Plan based on design specification
  • Develop constrained-Random verification environment for complex DUT
  • Implement coverage matrix using cover point and assertion
  • Create and debug tests for DUT
  • Resolve bugs with remote designers
  • Possess at least a Diploma, Advanced/Higher/Graduate Diploma, Bachelor's Degree, Post Graduate Diploma, Professional Degree, Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent
  • 5 years of hands on experience with SystemVerilog/UVM
  • Strong understanding of verification process from test plan to coverage completion
  • Strong communication and Analytical skills
  • Understanding of HDL (Verilog, VHDL)
  • Experience with designing with FPGA using Vivado is a plus

Interested Applicants:

Kindly send your detailed resume in MS Word format (Indicating Reason of Leaving, Availability Period, Last Drawn & Expected Salary) to

Selina Lim Siew Yen

Personnel Reg No: R1333126

EA Licence No: 02C3423

We regret that only shortlisted candidates will be notified

Selina Lim Siew Yen EA License No.: 02C3423 Personnel Registration No.: R1333126

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