- Responsible for developing optimal circuit solutions using advanced technology nodes that enables better design performance, with improved area/power tradeoffs
- Responsible for developing of standard cell source database and to perform cell modelling, which includes timing, functional and power models etc
- Responsible for developing and updating the standard cell design regression flows
- Engage with design teams to understand new library cell requirements such as static timing analysis, EMIR and P&R requirements
- Maintenance of the standard cell source database and regression platform
- Verification of functionality, performance, and power of all deliverables
- Evaluate best in class EDA tools in the industry
Requirements:
- Have a solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
- Understanding of layout at the transistor level in order to effectively work with the mask design team. Familiarity with reviewing DRC and LVS results an added plus.
- Understanding or an ability to learn a wide variety of industry standard modeling formats including Liberty, Verilog, LEF, Milkyway, APLs, SPICE.
- Familiar with working in Linux environment
- Familiarity with SKILL programming, load sharing concepts (such as LSF) and version control (such as ICManage) an added plus
- Experience designing or a solid understanding of standard cell architectures, including state retaining elements like latches and flops is highly desirable
Yvonne Ong EA License No.: 02C3423 Personnel Registration No.: R1549551
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