- Work closely with design team and make sure DFT structures are correctly inserted.
- Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
- Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
- Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
- Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
- Assist in Diagnosis and Yield enhancement through product lifecycle
- Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management
- MS or Ph.D. in Electrical/Electronic/Computer Engineering
- Minimum 8 years of experience as DFT engineer
- Experience in creating and implementing complex chip-level DFT architecture
- Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
- Knowledge of MBIST is a plus.
- Proficient in logic design using Verilog and experience in synthesis and STA
- Experience in developing test benches and simulation in RTL/GATE/SDF environments
- Knowledge of FPGA synthesis and design flow is a plus
- Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
- Strong technical ability to lead a team of engineers
- Good communication skills, works well in a group environment that spans across continents
- Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
Yvonne Ong EA License No.: 02C3423 Personnel Registration No.: R1549551